Projects
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Organization
Projects can be done alone or in small groups. The projects can be done in the TI LAB or at home. We will provide the necessary additional hardware (i.e. FPGA board).
You can earn one or more of practical Zeugnisse or work on your Master thesis (Diplomarbeit). If you are interested in one of the listed projects or have your own ideas for SoC related work contact Martin Schoeberl.
For ongoing and finished projects see:
Master thesis (Diplomarbeit)
Info on formal aspects of the thesis: http://www.informatik.tuwien.ac.at/studium/richtlinien/
Transactional Memory
Hardware transactional memory systems ([1], [2]) are a promising idea for future CMP systems. Within this master thesis a TM system will be implemented in a FPGA. It will be evaluated with a CMP version of JOP and optional a CMP of RISC cores.
- Synchronization solution for CMP
- Small buffer for each core
- Atomic commit (single token)
- Abort conflicting transactions on commit
- Implementation on the JOP CMP
Time-predictable VLIW
- Only WCET analyzable features
- E.g. method cache
- Compiler scheduled speculation
- Predicated instructions
- Cooperation with CompLang (Florian Brandner)
Safety critical Java on JOP
- Java the language for future SC applications
- Subset of Java
- Subset of RTSJ
- JSR302 standard
- About to finish
Virtual Memory Management with GC Interaction
Standard page mapped virtual memory is not the best fit for a garbage collected heap. This thesis shall investigate new organizations of virtual memory (with a hard disc or NAND Flash next level memory) that better interact with garbage collection. The assumption is a Java virtual machine (JVM) that runs without an OS on the bare metal. We can also change the processor if a new abstraction of the address translation is needed.
Worst-case cache analysis
Analysis of the "method cache" http://www.jopdesign.com/doc/jtres_cache.pdf and a standard direct mapped cache.
RTSJ on JOP
Implementation of the Real-Time Specification for Java (http://www.rtsj.org/), or part of it, on JOP.
ADA on JOP
Ada can be compiled by "JGNAT" (http://gd.tuwien.ac.at/languages/ada/gnat/jgnat/jgnat-1.1p/) to standard Java .class files. The task is to get ADA running on JOP by extending the current JDK for JOP to be compatible with JGNAT.
Project work (Bachelor thesis) and or Project (PR)
Some of the projects can also be extended for a Master thesis.
Transactional Memory Examples
Collection and implementation of multi-threaded Java applications that use atomic regions (transactional memory) as their only synchronization primitive. Evaluation of the performance on a TM Java processor platform.
Java processor comparison
Comparison of various embedded Java systems (e.g. aJile, Cjip, ARM/Jazelle, Komodo, FemtoJava, JOP,...) with respect to real-time capabilities, performance, and size (see also JavaBenchEmbedded). We have several embedded Java development kits available.
JTAG User Interface
The JTAG interface in an FPGA devices can also be used to connect to user logic. With this interface program download and debugging can be performed without the need for an additional serial interface. Tasks: Access to the JTAG port in a Cyclone device (VHDL) and PC software to drive the JTAG port (Java, http://bleyer.org/jjtag/).
JVM Test Framework
Test cases to verify that an implementation of a JVM (Java Virtal Machine) confirms to the "JVM Specification" http://java.sun.com/docs/books/vmspec/2nd-edition/html/VMSpecTOC.doc.html (Java).
Java TCP/IP
A TCP/IP stack written completely in Java based on http://www.jopdesign.com/ejip/index.jsp. API for the TCP/IP stack as in "javax.microedition.io" http://developers.sun.com/techtopics/mobility/midp/articles/genericframework/, part of "CLDC" http://java.sun.com/products/cldc/index.jsp. The TCP/IP stack has to be implemented for real-time applications (time predictable code and memory usage).
